New Electronics

Low source/drain contact resistivity for PMOS transistors

In 5nm and 7nm nodes, the source/drain contact area of the transistors is so small that the contact resistance threatens to result in suboptimal transistor functioning. Researchers have therefore been ...
Electronics Weekly

X-Fab adds 375V nmos and pmos super-junction transistors to BCD chip process

X-Fab Silicon Foundries has added 375V power transistors to the devices available from its 180nm deep trench isolation BCD-on-SoI platform chip fab. The second generation of its XT018 super-junction ...
Electronics Weekly

Updated: X-FAB adds to low-noise transistor portfolio

X-FAB has added three new low-noise transistors to its 180nm process node: a 1.8 V low-noise NMOS, a 3.3 V low-noise NMOS and a 3.3 V low-noise PMOS – all of which offer drastically reduced flicker ...
Nature

Analog Circuit Design Using MOS Transistors

Analog circuit design using MOS transistors represents a dynamic and rapidly evolving field that is integral to modern electronics. Exploiting the inherent advantages of MOS technology—such as ...
IT-Online

Intel demonstrates next-generation transistor scaling

Intel has unveiled technical breakthroughs that maintain a pipeline for the company’s future process roadmap, underscoring the continuation and evolution of Moore’s Law. At the 2023 IEEE International ...
CRN

IBM-AMD, Intel Describe 65-nm Transistors

Intel is in production with several 65-nm processors now, creating an inventory of commercial microprocessor products that will begin shipping early next year. At the IEDM conference, Intel showed die ...