EDN

Cache and Memory Hierarchy Design

• Designed a generic Cache simulator module and modeled L1, L2 caches augmented with a Victim Cache. • Implemented using C++ and evaluated with SPEC address traces for gcc, perl, vortex, compress and ...
Nature

Cache Performance and Memory Hierarchy Optimization

The dynamic interplay between processor speed and memory access times has rendered cache performance a critical determinant of computing efficiency. As modern systems increasingly rely on hierarchical ...
Semiconductor Engineering

Redesigning Core and Cache Hierarchy For A General-Purpose Monolithic 3D System

A technical paper titled “RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory” was published by researchers at ETH Zürich, KMUTNB, ...
Design-Reuse

Co-Designed Cache Coherency Architecture for Embedded Multicore Systems

One of the key challenges in chip multi-processing is to provide a programming model that manages cache coherency in a transparent and efficient way. A large number of applications designed for ...
EDN

Cache and Memory Hierarchy Design

Developed a flexible cache simulator which implemented L1 cache, its Victim cache and L2 cache. Analyzed the performance of various memory hierarchy configurations with varying parameters and ...