Electronic Design

Optimal Jitter Attenuation Starts With The Proper PLL Bandwidth

Clock signals provide reference timing to every integrated circuit and electrical system. Consumer applications typically use simple quartz crystals for reference clock generation. Other applications, ...
EDN

SOC-PLL design requires trade-offs

PLLs (phase-locked loops) are common analogcircuits in SOCs (systems on chips). Almost allSOCs with a clock rate greater than 30 MHzuse a PLL for frequency synthesis. However, a“one-size-fits-all” PLL ...
Design-Reuse

Selecting PLLs for ASIC Applications requires tradeoffs

Phase-Locked Loops (PLLs) are commonly used to perform a variety of clock processing tasks, such as clock frequency multiplication and clock deskewing. PLLs, like many other analog IP macros, come ...
EDN

Good behavioral model simulation: key to predicting first-order PLL synthesizer performance (Part 1 of 2)

In this article, the phase noise of a closed-loop, phase-locked loop (PLL) synthesizer is simulated using Agilent RF Design Environment (RFDE) and Advanced Design System (ADS) tools. The critical ...
Design-Reuse

True Circuits Introduces Spread Spectrum and Low Bandwidth Phase-Locked Loop Hard Macros

LOS ALTOS, California, May 5, 2003 – True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor and systems industries, today announced ...