Electronic Design

Phase-Noise Modeling, Simulation, and Propagation in Phase-Locked Loops (Part 3)

Some brief theory and typical measurements of phase noise. How to produce the lowest phase noise at a PLL output. A standard design procedure for a typical Type 2, second-order loop. As stated in ...
EDN

Simulating phase-locked loops (PLL)

I ran across a really good article about simulating phase-locked loops in Wireless Design and Development magazine. Andy Howard wrote it over at Agilent. Phase lock loops or PLLs are a very difficult ...
EDN

Improve phase noise by down-converting the VCO frequency

Phase noise is a critical parameter in most phase-locked loop (PLL) synthesizer applications. In radars, for example, phase noise at low-offset frequencies translates to the ability to discern between ...
Electronics Weekly

Great phase-locked loop motor control app note

Related to my search for reduced motor noise (and thanks to all who have made suggestions – ‘scope avaunt this weekend), is a search for speed stability in that motor*. And to someone who is in love ...
Electronic Design

Phase-Noise Modeling, Simulation, and Propagation in Phase-Locked Loops (Part 2)

Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...