Traditionally static timing analysis (STA) is used to verify if a CMOS digital design can meet the target speed at various process and interconnect corners. In practice, the worst-case slow or ...

San Mateo, Calif. – InTime Software Inc. will unveil a register-transfer-level timing tool this week intended to help IC designers develop timing-accurate RTL code before they move to synthesis, ...

Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is ...

Synopsys is claiming a 5-10x speed-up and 5-10x capacity increase for static timing analysis (STA), with no loss of accuracy. The enhancement comes from a tool called HyperScale within the 2010.06 ...

Nanometer design will require new thinking in timing closure. Historically, design teams relied on static timing analysis, which depends on the abstracted behavior of individual gates to perform ...

Magma's Tekton static timing analyzer is a next-generation tool built to handle the exploding number of STA scenarios required in modern SoC design. Static timing analysis (STA) is used throughout ...

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from ...

As the electronic design industry continues to push the limits of Moore's Law, a paradigm shift in timing analysis must be considered. The major reason for this is overly pessimistic timing analysis, ...

About five years ago if you listened to the marketing messages in the EDA industry, you would have thought it would be impossible to produce chips without statistical static timing analysis (SSTA).