EDN

Mentor Unveils FPGA Design-Flow Plans

Mentor Graphics is exploring the application of formal verification techniques in an FPGA design flow. Formal verification is recognized in the application-specific integrated circuit (ASIC) market as ...
Design-Reuse

Xilinx, Verplex Collaborate to Provide Formal Verification At Various Stages of FPGA Design Flow

SAN JOSE & MILPITAS, Calif.--(BUSINESS WIRE)--Aug. 27, 2001-- Xilinx, Inc. and Verplex(TM) Systems, Inc., today launched one of the first formal verification environments specifically for the design ...
EDN

FPGA synthesis can be a leverage point in your design flow

FPGA design starts are on the rise due to the lower startup costs and re-programmability that FPGA devices can provide. However, large, complex FPGA devices pose significant challenges to an FPGA ...
Electronic Design

Xilinx And Synopsys Collaborate On Tool Flow For Platform FPGAs

Time-saving verification tools have been added to an advanced tool flow for high-end FPGA design. The flow, a collaboration between Xilinx Inc. of San Jose and Synopsys Inc. of Mountain View, Calif., ...
CIOL

FPGA synthesis soln from Synopsis

BANGALORE- Synopsys Inc. has announced Design Compiler(R) FPGA (DC FPGA), a new FPGA synthesis product targeted for designers who prototype ASICs using high-end FPGAs. Built upon Synopsys' Design ...
New Electronics

Addressing safety critical FPGA designs

Field-programmable gate arrays (FPGAs) are the dominant hardware platform in many safety-critical, low-volume applications, including aerospace and nuclear power plants (NPPs). Modern FPGA devices ...