Design-Reuse

Creonic to Supply New LDPC Decoder and Encoder IP Cores for CCSDS Standard

Kaiserslautern, Germany, Apr. 30 2015 – Creonic GmbH, a leading IP core provider for communications, announced today the release of their new CCSDS LDPC encoder and decoder IP cores for the satellite ...
Design-Reuse

Creonic to Provide Three LDPC Decoder IP Cores for DOCSIS 3.1

Kaiserslautern, Germany, Oct. 28, 2015 - Creonic GmbH, a leading IP core supplier for communications, revealed today the availability of three IP cores for the new DOCSIS 3.1 standard. DOCSIS 3.1 ...
Total Telecom

AccelerComm’s New Highly Optimised LDPC Decoder in Software for Intel’s FlexRAN Reference Software Will Increase 5G Throughput by up to 3X

AccelerComm, the company supercharging 5G with Optimisation and Latency Reduction IP, today announced they have developed a highly optimised LDPC software decoder in collaboration with Intel. The ...
EDN

Low power LDPC decoder created using high level synthesis

HLS methodology allows the hardware design to be completed at a higher level of abstraction such as C/C++ algorithmic description. This provides significant time and cost savings, and paves the way ...
Total Telecom

AccelerComm Unveils Fully Integrated PUSCH Decoder to Supercharge 5G NR for Performance-Critical Channels

AccelerComm, the channel coding specialist, is supercharging 5G NR with cutting edge Physical Layer IP which increases spectral efficiency and reduces latency. The company today announced a complete ...
New Electronics

AccelerComm develops LDPC Decoder for Intel’s FlexRAN

AccelerComm, the company specialising in optimisation and latency reduction IP, has announced they have developed a highly optimised LDPC software decoder in collaboration with Intel. The solution is ...
Electronic Design

Low-Density Parity Check Error Correction for Solid State Storage

Error Correcting Code (ECC) technology, such as Low-Density Parity Check codes, has been around longer than most of you reading this have been alive. The reason is ...